XML CO527 Anonymous Questions and Answers

This page lists the various questions and answers. To submit a question, use the anonymous questions page. You may find the keyword index and/or top-level index useful for locating past questions and answers.

We have taken the liberty of making some minor typographical corrections to some of the questions as originally put. Although most of the questions here will have been submitted anonymously, this page also serves to answer some questions of general interest to those on the course.

Question 21:

Submission reference: IN2026

Are we allowed a calculator in the exam?

Answer 21:

Yes; the rubric, which you will have been made aware of, states that an approved calculator is required.

Keywords: exams

Question 22:

Submission reference: IN2027

From the self-test questions in Lecture 3:

Assuming the following:

• the TLB holds 64 entries and is initially empty
• the time required to load a PTE from memory into the TLB is 15ns, and the overhead for other read/writes on real memory is 10ns
• the translation time for virtual-to-physical addresses (when the relevant PTE is in the TLB) is 5ns

Calculate the memory-management overheads (in time) for a 1024-page virtual machine to access all of its pages (which are all held in page frames) at least once.

time = 15 +10 + (5 *(1024/64))= 105ns

Is this right and if it is not please direct me to the right way.

Answer 22:

This isn't quite right, but looking at the slides, I think the question may be slightly wrong anyway! The last bit ought to read ... to access all of its 4-byte words ... (rather than pages). With the question as it stands, the answer is moderately straightforward — the VM just accesses one location in each page once. To do that, the PTE must be loaded into the TLB (15ns), the physical address must be obtained (5ns) and then the real read/write on memory must occur (10ns). So each page access takes at least 30ns. Multiply that by the number of pages (1024) to get the total time: 30.7us. The fact that the TLB has 64 entries in this case is irrelevant, as each loaded entry is only ever used once.

Keywords: paging

Question 23:

Submission reference: IN2029

I am doing the 2009 paper and I have come across a similar problem to the one from Question 19 (2010), in particular the question about preemptive scheduling, is there any information on this in the slides?

Answer 23:

It is something that has been mentioned in the lectures and is present in the slides (even if not identified explicitly as such). Basically it's the literal meaning, i.e. the scheduling of some process preempts another. A typical example is when the network card generates an interrupt in response to a packet being received and the interrupt handler (or higher-levels in the device driver or network stack) arranges for the (blocked) process waiting for that packet to run immediately, rather than moving that process to the back of the run-queue and getting its turn eventually. Thus, the scheduling of that particular process preempts whatever process was currently running when the interrupt occurred.

Keywords: preemptive-scheduling

Question 24:

Submission reference: IN2028

I'm having trouble with question 1 (part d) in the 2010 past exam paper:

In many modern computer systems, paging is used in conjunction with segmentation, to combine the best features of both. However, the virtual address format and segment table structure are typically different from those shown above. Assuming that you are in a position to influence the design of such architectures (combined segmentation and paging) speculate on and describe:

I have looked at the slides on the subject but cant tell how the |4|16|12| bit set up for addresses works. I know the 4 bits is the segment entry number but do not know what information it stores or the purpose of the other bits. Any help on the situation would be greatly appreciated.

Answer 24:

Slide 55 in lecture 4 has the complete picture, which was explained in the lectures. In segmentation with paging, the virtual address is split into a segment number, a page number and an offset, in the examples with 4, 16 and 12 bits each respectively. The segment number is used as an index within the segment-table. The corresponding segment-table entry (STE) specifies the location of the page-table for that segment. The page number (middle 16 bits) is then used as an index into the page-table to find the actual page-table entry (PTE) for the page, and thus, the page-frame number (PFN). The offset is added to the page-frame number to produce the real address.

Keywords: segmentation , paging