XML CO527 Anonymous Questions and Answers

This page lists the various questions and answers. To submit a question, use the anonymous questions page. You may find the keyword index and/or top-level index useful for locating past questions and answers.

We have taken the liberty of making some minor typographical corrections to some of the questions as originally put. Although most of the questions here will have been submitted anonymously, this page also serves to answer some questions of general interest to those on the course.

Question 1:

Submission reference: IN1862

What is the average air-speed velocity of an unladen student?

Answer 1:

About 145 m/s.

Question 2:

Submission reference: IN1970

The instructions for starting the quiz say:

Once logged into raptor, execute: 

 /usr/l/frmb/co527/assess1/aqwrapper

(i.e. just type that in at the command-prompt and hit return)...

When I try this, I just get an error telling me that there is no such file or directory. What am I doing wrong?

Answer 2:

Almost certainly mistyping it. Try copy-and-paste rather than hand-typing. Make sure your slashes are the right way around (forward) and that the "/l/" bit is 'l' (El) as in "lillypad", not the number one. The typewriter fonts of some browsers make '1' and 'l' hard to distinguish.

Keywords: coursework

Question 3:

Submission reference: IN1971

Hello, do the questions for Assessment 1 for CO527 Operating Systems and Architecture change every time you take the assessment? Thank you.

Answer 3:

Yes; they are randomly picked from a collection of questions. However, the questions are weighted according to difficulty, so you might get [randomly] lots of easy questions or slightly fewer hard questions.

Keywords: coursework

Question 4:

Submission reference: IN1974

How do you login into raptor? I have set up my password but have no idea what to log into. If raptor is a software package it's not installed on campus where I am. Do I need to download putty to login?

Answer 4:

You're correct in that you need to download (and use) putty to login to raptor. putty is just an SSH client, so any other SSH client would do (putty is free and works pretty well though). If you're on a Unix or Linux system, just use the "ssh" command to login.

As mentioned in the first OS lecture, raptor is a Sun Enterprise server located in the machine room, thus the only way to login is remotely (via ssh).

Keywords: coursework , raptor

Question 5:

Submission reference: IN1990

I was assigned to research Sun's original UltraSPARC architecture for module CO527.

The trouble is I have searched the internet but I keep finding information about later architectures such as UltraSPARC II and III but not for the original UltraSPARC... I have also taken on loan the SPARC architecture manual but again it is no use to me...

My question is could you please recommend me a book title or place where I can find descent amount of information about the architecture?

Answer 5:

Wikipedia has a decent amount of information about the SPARC family generally, and in particular, the Sun UltraSPARC processor. Because "UltraSPARC" refers to a whole family of processors that started with the first one (which you're investigating), try searching for the specific part, rather than the name. E.g. Google finds some useful stuff for "Sun STP1030 datasheet" (STP1030 being the part number for that particular processor).

Keywords: ultrasparc

Question 6:

Submission reference: IN1991

Hello. I have a question regarding the architecture chosen for me (Sun UltraSPARC). I have been reading some material, but I thought I should ask if I am studying the correct chip. Was the original Sun UltraSPARC created in 1995 - 1996 implemented with the V9 instruction set? This might seem like a silly question; should I be concentrating more on the instruction set architecture, or the chip in general including the instruction set architecture.

Answer 6:

Yes, that's the correct chip. The focus should be more on the hardware architecture and less (or none) on the way it's programmed (SPARC V9 ISA). The example for the Pentium I provided should give you some idea of what's expected. You get three attempts at the quiz as well, so you could use the first attempt early to see what sort of questions it throws at you :-).

Keywords: ultrasparc

Question 7:

Submission reference: IN1998

Can you explain what big-endian and little-endian organisation is again, having looked over the slides and the diagram I cannot make any sense of what they mean. Thanks.

Answer 7:

It's the way that words (16 or 32 bits or larger) values are stored in memory, which is essentially accessed in 8-bit quantities. In the slides, a 32-bit value (let's say 0x1234abcd) is shown stored in little-endian and big-endian order. In little-endian, the least-significant-byte goes first, so at addr you would find 0xcd, at addr+1 0xab, at addr+2 0x34, and at addr+3 0x12. Big-endian is the other way around, i.e. the most-significant-byte goes first. Little-endian is probably more intuitive (and more common for CISC machines). Which byte-ordering is used can affect programs if programmers are not careful, particularly in C. You can write a simple test program, e.g.:

#include 
int main (void)
{
  int val = 0x1234abcd;
  char *vp = (char *)&val;

  if (*vp == 0x12) {
    printf ("Big endian!\n");
  } else if (*vp == 0xcd) {
    printf ("Little endian!\n");
  } else {
    printf ("Something else..?\n");
  }
}

Keywords: endianism

Question 8:

Submission reference: IN1999

I've just done one of the quizzes and I'm having a lot of trouble with the questions that give you the page-size, X-bit page table entries and ask how much virtual memory is addressable given the page table size.

I thought you would use the formula "VA = (PN x pagesize) + OFFSET", but I don't understand how to use that forumla with the values we are given.

Answer 8:

You're right in that you can't use that formula (for virtual-address) which just describes how the VA is composed of a page-number, page-size and offset. The questions vary in what they ask, but for the example you give:

From the VA formula, the maximum virtual address (i.e. size of virtual memory "vmax") must depend entirely on the page-number and page-size. The number of pages (page-number limit) depends on how many bits are available for it, with two raised to that power — check your CO324 and CO527 notes on binary arithmetic if that made no sense! E.g. if you have 5 bits for the page number, you can have at most 2⁵ = 32 pages (numbered 0 to 31). If each page is, say, 64 bytes big, then you can have at most 32 * 64 = 2048 addressable bytes. So the answer in this case would be 2 KiB (or 2048 bytes). Be aware that some questions talk about virtual-memory whilst some talk about physical memory, and the two are similar (for these types of question) but different.

Keywords: paging

Question 9:

Submission reference: IN2006

using a description of machine states and how a disk can be virtualised in such a system, how is the virtual machine concept is used in the IBM z/VM operating system, and how does it differ from its use on most other systems?

Answer 9:

It's not clear what you are asking.

If it's that you don't know the answer, don't worry. You haven't had that lecture yet!

Question 10:

Submission reference: IN2007

for the final question in assesment 4, i have found the flowers block and gone to the 3rd block, is the question simply asking for the value at 0x02 in the third block?

Answer 10:

Yes.

Question 11:

Submission reference: IN2010

Please could you change how Moodle displays the module content. Having to use the selector gets rather annoying. I would like it if, like other modules, the content is displayed on one page. This would save valuable time! Thanks in advance.

Answer 11:

This is not a module thing — mine appears all one one page :-). There's a box somewhere on the top-right of the currently display content box that makes the rest of them visible. I'd agree that the user-interface in this respect could do with more effort, having had a similar issue myself.

Keywords: moodle

Question 12:

Submission reference: IN2015

Just a quick Operating Systems related question! How do you determine the maximum size of a segment given an 8-bit segment number in a 32-bit VA? (Question 1A 2010 Paper)

Answer 12:

The maximum size is determined by how big an offset you can have as part of the virtual-address, which in this case is 24-bits (32 - 8). Thus, the maximum size is 2²⁴ bytes, or 16 MiB.

Keywords: segmentation

Referrers: Question 15 (2010)

Question 13:

Submission reference: IN2017

How can you determine between an Operating System's features and its characteristics? So whether concurrency is a feature or characteristic.. etc.. Thanks.

Answer 13:

From 2008 onwards, we haven't distinguished between these. Characteristics are exhibited behaviours/properties, so concurrency, sharing, long-term storage and nondeterminacy are characteristics. Features are inherent properties, including efficiency, reliability, resilience, maintainability and small-size.

Keywords: exams , features , characteristics

Question 14:

Submission reference: IN2000

Hello, what are the three main states in which a process could exist? As far I know a process could be in a running state, blocked state and I am not sure about the last one. I am guessing it is either descheduled or sleep-state. Thanks.

Answer 14:

A sleep-state implies the process is waiting for something, and is thus blocked. The first two states (running and blocked) are two of them. The third is on run-queue, where the process is ready to run but the CPU is busy executing another process (one that must be in the running state). The term 'descheduled' would normally be used to describe the transition between states (e.g. running-to-blocked or running-to-run-queue).

Keywords: processes

Question 15:

Submission reference: IN2018

Hello, I'm trying to calculate the size of a particular segment, I'm looking in the notes but not finding anything in the notes that helps me. Can you please tell me how to calculate the answers to the questions below?

1. Assuming that the segment number occupies the top 8-bits of a 32-bit virtual address, what is the maximum possible size of any particular segment? (you may give your answer in terms of MiB, KiB or bytes).
2. Assuming that each segment table entry is 48-bits (6 bytes), how much space is required for the whole segment table?

Can you please tell me how to do these questions because I'm really stuck.

Answer 15:

For the first, see Question 12 (2010). The second is similar — the segment number is 8-bits, so there can only be 2⁸ = 256 different segments. If each Segment Table Entry (STE) is 6 bytes, then 6x256 = 1536 bytes are required for the whole segment table (or 1.5 KiB).

Keywords: segmentation , exams

Question 16:

Submission reference: IN2020

Hi, I've been going through past papers & lecture slides and I have a few questions about multi-core/processor machines.

1. Would I be right in saying that since from the diagram on the slides Pentium processors appear to share their L2 cache, RAM accesses aren't cached local to a core so processes gain no performance from being scheduled to the same core as much as possible, or am I wrong in thinking that the cache is shared — perhaps it is the bus to the cache that is shared, with the cache divided up into sections for each core, just not stored on each core?
2. Similarly the slides say that AMD processors have to worry about page frame allocation more than Intel ones due to them having a non-uniform memory architecture. This seems to indicate that cores in AMD processors have fast, local RAM that only they can access — is this just the on core L2 cache? I always thought that the cache just, well, cached memory writes / accesses, so using some kind of virtual memory system for the cache seems a little odd, unless it just tries to maintain a local duplicate of relevant page frames in RAM? I'm probably fundamentally misunderstanding something here...

Thanks!

Answer 16:

1. A multicore package will probably share the L2 cache, but each core still has its own L1 cache. Of course, you might not be using a multicore machine (and just using regular multiprocessor), in which case there's L1 and L2 caches per core. As far as cache-affine scheduling in multi-processor multicore machines goes, it's probably wise to try and schedule the process on the same group of cores.
2. Whilst AMD (and now QPI based Intel machines as I mentioned in the lectures) have local and non-local RAM, any core can access any memory; it's just that non-local RAM costs more (in time) to access. From the diagram in lecture 5, non-local memory reads/writes come in over the hyper-transport bus (or QPI on modern Intels) and get routed to the memory, rather than up to the processor/core.

Keywords: multiprocessor

Question 17:

Submission reference: IN2019

Ok, so I've been checking out the past papers, and I was looking at the 2008 paper. For Question 5, the last part. The speed for when a process is via pipeline is kt+(n-1)t, but for this question it is asking to compare 2 different processors each with a different number of stages (k) is 8 or 3 but instructions (n) is 10 for both.

For the speed of the processor:
2GHz = 8t + 9t = 17t
1GHz = 3t + 9t = 12t

but the ts are different... so we would perhaps scale up? for 1 GHz now 12*2t, so:
2GHz= 17t
1GHz= 24t

Would this work and then 24/17 = 1.4 something... Or is something a bit more complicated taking into consideration more the fact that the first processor is twice as fast, but has 8 stages, and the 2nd processor is half the speed of the first, but only has 3 stages?

So perhaps something like...
(24/3)/(17/8)=
8/2.125 = 3.61

I am really unsure how to tackle this, its a tricky question and one I really wouldn't have expected given the quizzes and the practice lecture examples... Am I over-complicating or misinterpreting the question?

Any advice would be much appreciated, Anonymous ;)

Answer 17:

I think you're over-complicating this. The question asks you to compute the speed-up factor for two things, the 2 GHz 8-stage pipeline and the 1 GHz 3-stage pipeline, and then compare them.

I would start by computing the speed-up factor for both, using the given formula:

S = n.k.t / (k.t + (n-1).t)

You can obviously cancel out the ts here, giving a simpler:

S = n.k / (k+n-1)

For the first, plug in k=8 and n=10, which gives a speed-up factor of S=4.7 (roughly). For the second, plug in k=3 and n=10, which gives a speed-up factor of S=2.5. You could then state that the first architecture has a speed-up of almost twice the second. Given that the question is asking you to compare speed-up factors, and not absolute computation times, I'd probably stop at that point.

If the question wanted you to compare the execution times for the two architectures, it would state that explicitly. In that case, you would use just the bottom half of the formula, i.e. "k.t + (n-1).t", as the time required for n tasks through a k long pipeline at t time units per step. Dealing with nano-seconds (doesn't matter what order of magnitude you pick here, but that would be the most obvious), for the first architecture you plug in k=8, n=10 and t=0.5 to give 8.5 nano-seconds. For the second, plug in k=3, n=10 and t=1 to give 12 nano-seconds. To get the comparison, just divide these, which gives you the 1.4 you had. However, the question isn't asking this..

Keywords: speedup , speed-up-factor

Question 18:

Submission reference: IN2021

Could you please go over what a cache disable bit is for and when it would be advantageous/when to use it? Thanks

Answer 18:

The cache disable bit (on architectures that support it) disables the processor's caching of that particular page. In most cases (i.e. normal code/data) you would not want to use it, as it nullifies any advantage the processor cache gives. Places where you would want to use it include framebuffer memory (since a cache only speeds up memory reads and a framebuffer is pretty much write-only) and memory-mapped I/O devices (since these are not memory/RAM in the conventional sense).

Keywords: paging , cache

Question 19:

Submission reference: IN2023

Hi, I'm looking at the past exam paper for 2009 and for Q2 Part C I am unsure of the answers. I've made a guess of what states are represented by X, Y and Z and as for the other parts of the Q I am completely at a loss for where to look for answers/how to analyse the data I've been given in the Q for all the remaining parts. For questions like this what do we need to look for to figure out if it is preemptive or non-preemptive scheduling? I would hope the answer is not actually "it is impossible to tell" for this Q but if it is, how would I be able to tell if it were possible? Thanks.

Answer 19:

In this particular case, any of the three is possible. The 3 marks come from your justification of why, which may depend on your answers for the previous two parts. Arguing for "impossible to tell" is probably the hardest to do convincingly. Arguing for "non-preemptive" is probably the easiest. Obviously you need to know what preemptive scheduling is and how it affects the scheduling of processes in response to particular events.

Keywords: exams , processes

Referrers: Question 23 (2010)

Question 20:

Submission reference: IN2025

Hey, I've been looking over the different page replacement strategies but have become stuck when looking at the layout of the inverse page-tables for each one. They can be seen on slide 58/102 on the Resources and Systems Under Load lecture (10). If you could explain the format of inverse page-tables shown and what the different numbers/columns correspond to it would be very helpful! Thanks.

Answer 20:

With the inverse page-tables, the first column just specifies which particular VM(page) occupies the page frame. The second column numbers are specific to the replacement algorithm in use — as you flick through the slides, these will change in response to the 'r' (referenced) bit set/not-set in the PTEs. The numbers in red by the side of the inverse page-table indicate the replacement order (always starting with the free page frame which, obviously, does not need evicting).

Keywords: paging