XML CO527 Anonymous Questions and Answers Keyword Index

This page provides a keyword index to questions and answers. Clicking on a keyword will take you to a page containing all questions and answers for that keyword, grouped by year.

To submit a question, use the anonymous questions page. You may find the keyword index and/or top-level index useful for locating past questions and answers.

Keyword reference for cache

Question 57 (2014):

Submission reference: IN3741

You would use the cache disable bit for memory mapped hardware right? I don't really know how to explain why though. Because it doesn't actually refer to memory and can't be treated as such, therefore it doesn't make sense to cache it? Or that its different each time and so cache doesn't make sense? Also, is it just memory mapped hardware you'd want to disable cache for?

Answer 57:

Memory-mapped I/O regions (e.g. PCI space) are sensible to cache-disable for the 2nd reason you give. The first "because it isn't memory" probably wouldn't earn you marks in an exam as it lacks an explanation as to why. But "different each time" is wrong (though some marks for that). The precise reason is that "it might be different each time it is read" and writes to I/O regions must go straight to the bus (e.g. timing requirements) and not be delayed in a write-back cache, for instance. Other memories that don't make sense to cache: graphics framebuffer. Or at an application-level, a clever programmer (who knows how their program works) could turn off cache for regions of virtual memory that they know aren't worth caching based on the access characteristics. You might also want to turn off caching to work out the performance gain the cache is giving you (but that's a more all-encompassing, less page-level, reason).

Keywords: cache , memory-management

Question 133 (2013):

Submission reference: IN3008

How does direct and fully associative cache work? I'm having a hard time understanding it, I've been through the slides and the lecture audio but it still doesn't help.

Answer 133:

If my explanations of these in the lecture slides and recordings aren't helpful, then me trying to explain it again here is unlikely to be that effective! I just Googled for "direct mapped cache" and a lot of the results look relevant; similar for the other I'd imagine. Finding things out for yourself is a useful (necessary even) skill :-).

Keywords: cache

Question 26 (2013):

Submission reference: IN2873

With set associative caching so if you do it 4-way can each bit of cache have different cached addresses on them, or do they all have to be the same?

Answer 26:

Each of the 4 caches can have different addresses (and data) cached — and necessarily so, else the collisions that a direct mapped cache experiences wouldn't go away! In a 4-way set-associative cache, there 3 other caches to choose from if 1 is already occupied on the particular line that address maps to.

Keywords: cache