|
CO527 Anonymous Questions and Answers |
This page lists the various questions and answers. To submit a question, use the anonymous questions page. You may find the keyword index and/or top-level index useful for locating past questions and answers.
We have taken the liberty of making some minor typographical corrections to some of the questions as originally put. Although most of the questions here will have been submitted anonymously, this page also serves to answer some questions of general interest to those on the course.
Submission reference: IN2999
Are the slides on D-Type Flip Flops and other digital logic things examinable?
See Question 119 (2013).
Submission reference: IN3000
On the slides for instruction encoding, there are 16 bits in total: 5 bits for dest-reg, 5 bits for src-reg, 3 bits for the operation code, what are the 3 bits at the front for? In the slides it's 001.
By process of elimination, it must be identifying the type of instruction, but you're not going to find questions like that in the exam: the architecture is hypothetical and asking you to remember specifics like that would be mostly pointless. For a real architecture, you'd use a data-sheet, and there's little value in memorising that for an exam! Of course, I'd expect you to understand that instructions do have structure and that certain bits of information are encoded in them, but what that information is can be worked-out from the context of the instruction.
Submission reference: IN3001
I'm having trouble answering this question:
"Assuming a page size of 2^12 (4096) bytes, how much physical memory is addressable in a system using paging of this style? (show your working)."
I know that each PTE is 4KB and a VM has 4gb of addressable memory. According to people I revise with I need to know the number of bits that contains a PFN. How would I calculate this?
To calculate the address space would I then divide the 2^12 by the answer of the PFN?
There's not enough information in what you've written to answer this: you need to know the number of bits allocated for a PFN in an individual PTE. That tells you how many possible page-frames can be addressed, and given you know the page size, you can easily work out the maximum amount of addressable memory.
Some other points: a PTE is not 4 KiB, it's about 4 bytes (depending on the system). Dividing the page size (4096) by something won't give you anything meaningful — certainly not if you end up with an answer of the form "there are 256 bytes of memory addressable", which would be daft given that most modern machines (using paging) have gigabytes of RAM! When you get an answer to this sort of thing, ask yourself if it makes sense.
Keywords: paging
Submission reference: IN3002
When will be getting our marks back for assessments 4 and 5?
As soon as I've marked them. I'm going through assessment 4 at the moment, interleaved with exam script marking. Sorry it's taking so long, but there are a lot and I'm loathed to give substandard feedback (certainly for assessment 4).
Keywords: coursework
Submission reference: IN3005
What's write through caching?
Hint: Google :-). You'll probably remember better if you look up facts like this for yourself, rather than me just giving you a rote answer..
Submission reference: IN3007
Going through the 2013 past paper, I can't seem to answer this question: Name three items that usually appear in a file system directory entry. Can you offer some help? Thanks.
Examples include:
Submission reference: IN3003
Within index-block file system organisation, does each file have one or more index blocks, or is there one or more index blocks, on the disk, which describe the structure of the blocks that make up all the files on the disk?
Each file has at least one.
Submission reference: IN3004
Regarding Distributed file systems, what is the difference between location transparency and migration transparency?
Migration transparency means that it can be moved without affecting users. It is really a superset of location transparency, to be honest.
Submission reference: IN3006
If one client, client1 has a exclusive oplock which client1 is using to modify data and another client client 2 comes along who also wants to modify data, who is the oplock given to ?
It's refused for client 2 as client 1 already has it, normally. Although that's general file locking. If they are both going to modify, neither of them has any oplocks and caching is thus turned off. Remember that oplocks are really about enabling safe caching.
Submission reference: IN3009
Within the architecture diagram (hypothetical AVR or related), what does [0-11] mean on one of the inputs to the the sign-extension unit?
This is referring to bits 0 through 11 (12 bits). In this case, the least-significant 12 bits of the 16-bit instruction (the most significant 4 bits would indicate that this is a jump/call instruction of some kind, given that the other 12 bits are used to update the program-counter).
Keywords: architecture
Submission reference: IN3010
On the complete core diagram what actually happens within the register-file, with regards to its inputs {00, 01, 10, 11}? Do these represent the two outputs, e.g. a 0 to the CCR and 1 to the ALU?
The particular multiplexer you refer to is one of the data inputs to the register-file. The particular selection (0 through 3, or the binary equivalents shown) determines where that data is coming from. If 0, it's the current value of the CCR; 1, something from the instruction (probably a load immediate to register, ldi); 2, something from the data-memory or I/O bus; or 3, a result from the ALU.
With regards to the first output on the right-top of the register-file diagram, this goes into a switch (2-way, so just 0 through 1). If 0, that output goes into the CCR; if 1, the ALU. In the first case (write register to CCR) this is probably for a specific instruction that allows the CCR to be written. The real AVR has instructions like sec, clc, etc. for handling individual bits in this; the hypothetical AVR shown cannot do this, instead it probably has a "wccr r16" type instruction for writing the CCR, and "rccr r16" for reading it (that would switch the register-file input to 0, with 16 (for r16) on the associated control-line (purple).
Keywords: architecture
Submission reference: IN3011
If you were to fail a exam (under 40%) but you passed the module overall (due to coursework) would you need to retake the exam?
No. If you pass the module overall (>= 40%) then you've passed and get the credit, regardless of how that works out (good exam, failed coursework or failed exam and good coursework).
For the majority, compensation will apply too, whereby you can pass with a mark of >= 30% overall, but only 30 credits can be compensated in this way (CO527 is a 15 credit module).
But best to revise hard and do your best to pass :-).
Submission reference: IN3008
How does direct and fully associative cache work? I'm having a hard time understanding it, I've been through the slides and the lecture audio but it still doesn't help.
If my explanations of these in the lecture slides and recordings aren't helpful, then me trying to explain it again here is unlikely to be that effective! I just Googled for "direct mapped cache" and a lot of the results look relevant; similar for the other I'd imagine. Finding things out for yourself is a useful (necessary even) skill :-).
Keywords: cache
|
Maintained by Fred Barnes, last modified Wed May 25 15:07:20 2016 |
