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CO527 Anonymous Questions and Answers Keyword Index |
This page provides a keyword index to questions and answers. Clicking on a keyword will take you to a page containing all questions and answers for that keyword, grouped by year.
To submit a question, use the anonymous questions page. You may find the keyword index and/or top-level index useful for locating past questions and answers.
Keyword reference for architecture
2014 |
Submission reference: IN3752
How do we have 16-bit values flying around the diagram of our processor near the program counter when it's just an 8-bit machine? Is it just that those particular address buses are wide enough to allow it, or are we using the value held in 2 8-bit registers?
This is explained in one of the OS lectures probably: the "8-bit"-ness of the machine (word size) refers to the natural size of computations in the device. But that doesn't preclude different bits of the architecture having more (or less) bits. The program memory is a 16-bit space (actually more on some devices) so the address busses involved here are suitably sized. The fact that the instructions come out of the program memory in 16-bit pieces is co-incidence (mostly). Because the registers are only 8-bits wide, when manufacturing a complete address in the program, you'll need to pair up 2 8-bit registers (which is kinda what the X, Y and Z register pairs are for).
As a fairly crude contrast, something like the Intel Pentium (old now), was a 32-bit processor, but had a 36-bit (physical) address space, 32-bit (virtual) address space, and the instructions in memory vary in size between 1 byte and 7 bytes (give or take).
Keywords: avr , architecture
Submission reference: IN3751
For the ATMega328, if the data address space 16 bits, that means there are 65536 addressable locations within it, each of which is 8 bits in size. So overall there is about 64kb of SRAM. I'm getting a bit confused. Am I right in saying that the data address space is only 16 bits when there is 64kb of SRAM, and if there was, say, 2kb of SRAM, the address space is just 11 bits?
There are two aspects here which you're confusing slightly. The first is the size of the address space, and as you point out, a 16-bit address space can address exactly 64 KiB (216) addresses. The second aspect is how much memory (SRAM) there actually is. So on something like the ATMega328, the address space is 16-bit, but only 2 KiB of it is actually occupied (attempts to access things in the remaining 62 KiB won't result in any sort of error, probably either garbage [random] data or mapped onto the 2 KiB SRAM repeatedly, which I think the AVR actually does, but check the datasheet if you want to be sure!).
Because the ATMega328 only has 2 KiB SRAM, you'd only need 11 bits of address space for practical purposes. If you look in the datasheet, some address-specific I/O registers only actually have enough bits as needed (e.g. the stack-pointer is 11 bits on the ATMega328, more on the ATMega2560 for instance).
Keywords: avr , architecture
Submission reference: IN3415
What would you suggest we do if we literally don't understand a thing you've been going on about in lectures?
Apologies for my lack of coherence yesterday (and advance warning for today!) but I'm not well :-(. And rescheduling lectures is not a practical option. In general though, and as I said at the beginning, attending the lectures is not enough: you need to be spending time outside the lectures (around 2 hours per lecture I'd say) doing your own reading and learning. I.e. recommended textbooks, Google, Wikipedia, etc. You should be looking to spend a whole day a week on CO527, given it accounts for 25% of your credits this term :-). The content of CO527 is deeply technical (not surprising given the topics) and staying on-top of it might be a struggle (it is a degree you're heading towards, not a GCSE or A-level, so it being difficult in places is not unexpected, and it's hard to be good at everything). Don't, however, make the mistake of thinking that if you memorise all mine and Bob's lecture slides you'll pass the module: most people will need to do more to effect learning.
If people have specific aspects they don't understand, or want clarification, then I'm happy to talk/explain! (if you can catch me in the office, else email, or anonymous questions!).
Keywords: architecture
2013 |
Submission reference: IN3010
On the complete core diagram what actually happens within the register-file, with regards to its inputs {00, 01, 10, 11}? Do these represent the two outputs, e.g. a 0 to the CCR and 1 to the ALU?
The particular multiplexer you refer to is one of the data inputs to the register-file. The particular selection (0 through 3, or the binary equivalents shown) determines where that data is coming from. If 0, it's the current value of the CCR; 1, something from the instruction (probably a load immediate to register, ldi); 2, something from the data-memory or I/O bus; or 3, a result from the ALU.
With regards to the first output on the right-top of the register-file diagram, this goes into a switch (2-way, so just 0 through 1). If 0, that output goes into the CCR; if 1, the ALU. In the first case (write register to CCR) this is probably for a specific instruction that allows the CCR to be written. The real AVR has instructions like sec, clc, etc. for handling individual bits in this; the hypothetical AVR shown cannot do this, instead it probably has a "wccr r16" type instruction for writing the CCR, and "rccr r16" for reading it (that would switch the register-file input to 0, with 16 (for r16) on the associated control-line (purple).
Keywords: architecture
Submission reference: IN3009
Within the architecture diagram (hypothetical AVR or related), what does [0-11] mean on one of the inputs to the the sign-extension unit?
This is referring to bits 0 through 11 (12 bits). In this case, the least-significant 12 bits of the 16-bit instruction (the most significant 4 bits would indicate that this is a jump/call instruction of some kind, given that the other 12 bits are used to update the program-counter).
Keywords: architecture
Submission reference: IN2995
Yesterday in the revision session, it was said that without absolute jumping you would not be able to go to addresses within -1023 — +1024 of the address, or up to 2048 from the address. Does this mean that the bootstrap wouldn't work as the code for the bootstrap is executed based on a known address?
Not necessarily: when powered on, presumably there is some initial PC value, so execution starts somewhere which will be known. The assembler (software that turns assembly source into binary blobs) knows where things are — it's creating a memory-image for the FLASH basically — and that starting-point can be specified using an ".org" directive.
The values you have aren't quite right though: the example in the revision session (from the mock architecture questions) takes 12-bits of address from the (presumably jump or call) instruction, bits 0-11 inclusive. 12-bits gives you 4096 distinct values, so when interpreted as a signed (2's complement) value, that gives -2047 through 2048 (still 4096 distinct values).
Keywords: architecture
Submission reference: IN2928
In the mock paper what does the JEnb signal do?
This is just an enable signal, "jump enable" in this case. The idea is that the comparator wouldn't look at its input, nor drive its output, until this signal goes high — i.e. the comparator should only be active at certain stages, not all the time.
Keywords: exam , architecture
Submission reference: IN2925
For the mock paper that was put up I was looking at the first part of question 2, am I right in thinking that the initial value 0x0200 is a relative jump forward 512? If so how would you work out the next instruction after 0x0FF0? Just add 1 bit?
Not quite — 0x0200 is the address where the instruction resides (i.e. the current program counter value). The instruction itself is 0x0FF0: i.e. this is the value that appeared on the dashed line in the diagram, part of which goes to the "sign-extend" unit, the comparator and anything else (not shown). From knowing what the instruction is, you need to figure out what happens with each of the internal components, and as a result, what the new program counter value will be. The question in this case asks you to "describe the sequence of actions", so you should be specific about what happens and when (part of the when is given in the question by the analyzer trace, which tells you how the internal components are orchestrated).
Keywords: architecture , exam
Submission reference: IN2889
On slide 11 of the lecture "AVR & Assembly Programming", what do you mean when you say that the instruction can't be encoded?
I thought the SRAM just contained data+registers for the instruction to use; why would the instruction be encoded onto it?
And what's X, Y and Z?
For context, the slide (talking about SRAM access) states: "need 16-bit (or at least 12-bit) addresses — not enough room to encode in instructions.". The issue here is that instructions themselves (e.g. load or store) cannot refer to SRAM addresses directly — there isn't enough room in a 16-bit instruction word to encode a 16-bit (or 12-bit) address (plus whether the instruction is a load or store and the target or source register).
SRAM just contains data — no registers, although the contents of the register file are accessible at SRAM addresses 0-31, this is a convenience for programming: when code accesses these locations, no real SRAM activity takes place (because the actual 2 kilobyte SRAM is mapped at addresses 0x100 to 0x8ff). However, there is nothing about encoding instructions onto it (that doesn't make technical sense), the issue as stated is how to represent the possible addressable locations (0x000 to 0x8ff) in a read or write (or other) instruction to be able to access this memory from the program.
The X, Y and Z registers are just particular names for pairs of 8-bit registers, that are used to provide 16-bit addresses. The main use being to access SRAM. I.e. you load a 16-bit address in two halves into the appropriate X, Y or Z register, then say to the CPU "load from address in X". That way the instruction only has to encode whether the address is in the X, Y or Z registers, not the actual address itself. Reading and understanding the various assembler examples (including those from the practical session) will help to put some of these aspects in context.
Keywords: avr , architecture
Submission reference: IN2650
What comes out of the switches on the "Construction: PC and Instruction Memory" slide? If br-rel goes in, how does the switch determine what goes out? Also, what is the difference between pc-adj and pc-set?
You need to understand the difference between signals and data here — br-rel and br-abs are control signals that set the multiplexors there one way or the other. What goes out is simply what went in on the appropriate input. In the case of the br-rel switch, if it's 0 then the output of that switch is just the incremented PC; if it's 1 then the output is the result of the addition between the incremented PC and the value presented on pc-adj. I'm just reading off the diagram here, which you should be able to to do for yourself! I did explain these in the lecture at that time, which is why I encourage you to take notes in lectures! :-).
The difference between pc-adj and pc-set: what they are used for. It's explained on the slide! If you need more guidance than this, ask one of your peers (preferred) or pop by my office sometime (S113).
Keywords: architecture
Submission reference: IN2648
What are pc-adj, br-rel, pc-set and br-abs from the second lecture?
These are explained in the slides for the second lecture! But the names are not so important (e.g. "br-rel" is for "branch relative"). More important is understanding the function, e.g. when br-rel is asserted (set to 1), understanding what the value on pc-adj is and how it changes the program counter (PC).
Keywords: architecture
2012 |
Submission reference: IN2393
I have been trying to do the past paper and I came cross this the type of question where I need to calculate the value held in the PC with branch instruction. A typical question would be:
The following diagram shows the bit values of a Branch if Not Equal instruction located at address 0x0000C000, and the contents of a selection of registers inthe Register File:
| op | rs | rt | offset | |000101 |00111|00001|0000000000010111|
with:
|register | contents | | R1 | 0x8000000F | | R2 | 0x00000C00 | | R3 | 0x00000C00 | | R4 | 0x000000FF | | R5 | 0x00018000 | | R6 | 0x000D00A0 | | R7 | 0x8000000F |
The question then asks me to calculate the value held in the PC following execution of this instruction. I tried to look through slides but all it tells me is a formula of "if (rs!=rt) then PC+offset".
I used this method and I cannot answer this question. I also tried to look and search for how to calculate this online but didn't manage to find any examples. Can you guide me through this kind question of how to calculate this?
The formula is essentially correct, though there are some bits that need to be taken into account (if you follow the MIPS datapath for this type of instruction you'll see what extra is needed).
Us simply telling you how to do this sort of question is probably less valuable than (together) figuring out where you're getting stuck so we can help you on that specific point; i.e. you would benefit more from coming to see one of us in person.
However, in summary, using the formula you have (though it's not correct in this context, but good enough for starters):
In this case the branch isn't taken (because the values are equal), but it's important that you understand how to approach this question, not just fill-in-the-blanks in a template answer (which demonstrates a lack of understanding).
Keywords: architecture
2011 |
Submission reference: IN2147
I have a question regarding Branch instructions. If I have a branch if not equal to instruction located at 0x00002000 (PC) and the following:
RS(Register 4) = 0
RT(Register 3) = 7
Therefore branch does not equal and should then follow the following equation:
if (rs!=rt) goto (PC+offset)
The PC is 0x00002000 and the offset is 0000000000001000.
What I have done is converted the offset to 32 bits which will just have an extra 16 0's to the left but I have no idea how to add the two and the lecture slides aren't particularly clear or give examples on how to do this... So I was just wondering how I could do this to get the new PC? Any help is much appreciated, Thanks!
The logic of what happens when the branch is taken isn't quite right. As Winston showed in the revision session earlier, you can reverse engineer what the new PC is based on the MIPS datapath diagram. Specifically, a constant 4 is always added to the PC, and the offset is always shifted-left 2 (to multiply by 4). So the equation you should be thinking about is:
new_pc = old_pc + 4 + (offset * 4)
But that's just simple arithmetic! The problem you're encountering is because the offset is expressed in binary (base-2) whereas the PC and register contents are expressed in hexadecimal (base-16). Converting between the two should be something you practiced well at stage 1. Once you've got the sign-extended offset in hexadecimal, the addition is trivial. You could convert everything to decimal (base-10), feed it into a calculator, and convert the answer back into hexadecimal, but that's particularly time consuming. On paper, the calculation would look something like:
old PC = 0x00002000 +
0x00000004 + (constant always added to PC, from MIPS datapath diagram)
[4 * 0x00000008] (offset 0000000000001000b sign-extended)
[ == 0x00000020] (shift-left 2 gives 0000000000100000b)
----------
0x00002024 (new PC)
Keywords: architecture
Submission reference: IN2109
Hi, I'm having trouble understanding exactly how branching offsets are used. In my example below (hopefully the formatting didn't break) when trying to jump forward 8 instructions, it appears that we end up 9 instructions along. Is there something I am missing?
Instruction | Instruction offset | ================================ 0 | ? 4 | ? 8 | BEQ 1 1 8 12 | (1st) 16 | (2nd) 20 | (3rd) 24 | (4th) 28 | (5th) 32 | (6th) 36 | (7th) 40 | (8th) <-- This is where I would expect to be, 8 instructions along. 44 | (9th) <-- This is where (8+4) + (8<<2) ends up.
It also means that branching with an offset of 0 would jump to the next instruction when to me it should be the current instruction.
If you look at the MIPS definition for the branch instructions, the offset (when branching) is applied to the instruction pointer, which will already have been updated to point at the next instruction, so will always be 1 word ahead of the current instruction. That gives the results you see; the bit of information you were missing is that the instruction-pointer has already been updated at the point the branch is processed (in practice anyway — logical diagrams may show this more explicitly as a +4 embedded into the branch path somewhere, depending on where the control signal for the branch is wired).
Keywords: architecture
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Maintained by Fred Barnes, last modified Wed May 25 15:07:20 2016 |
