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Implementation of the Veritas Design Logic
F. K. Hanna, N. Daeche, and W. G. J. Howells
In Proc. Theorem Provers in Circuit Design, pages 182-196. North Holland, 1992.Bibtex Record
@inproceedings{427,
author = {F. K. Hanna and N. Daeche and W. G. J. Howells},
title = {Implementation of the {V}eritas {D}esign {L}ogic},
month = {unknown},
year = {1992},
pages = {182-196},
keywords = {determinacy analysis, Craig interpolants},
note = {},
doi = {},
url = {http://www.cs.kent.ac.uk/pubs/1992/427},
booktitle = {Proc. Theorem Provers in Circuit Design},
publisher = {North Holland},
}