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CO527 Anonymous Questions and Answers |
This page lists the various questions and answers. To submit a question, use the anonymous questions page. You may find the keyword index and/or top-level index useful for locating past questions and answers.
We have taken the liberty of making some minor typographical corrections to some of the questions as originally put. Although most of the questions here will have been submitted anonymously, this page also serves to answer some questions of general interest to those on the course.
Submission reference: IN2845
where is the current file access state stored on distributed filing systems?
This was covered in the Tuesday lecture in week 23.
It depends on the file system. For NFS, the state is all on the client. For CIFS, it is on both the server and the client.
Submission reference: IN2859
What kind of score should we be aiming for on our disk scheduling implementation?
As best as you can get it, really! For reference, my fairly rapid (15 minutes) circular scan implementation reports 622 for requests.txt and 2330 for requests-big.txt. But the standard by which you'll be marked is yourselves, i.e. the best performing solution will get 100%, something that implements SSTF correctly will score around 50%, but the exact scaling/etc. will depend on the distribution of submissions. That is, exceptional solutions that way outperform anything else won't mean everyone else scores worse as a result!
Keywords: assess5-1314
Submission reference: IN2872
I've been doing the assessment today and have just started getting an error which I don't really understand. Could you explain what causes this error?:
...
highlevel_didread(): read queue 1 already done at time 5874032 (block 2457603)
...
highlevel_didread(): read queue 1 already done at time 5874053 (block 2433090)
...
It appears every time a block is returned from disk.
The most likely cause is returning a block more than once, which may be because that particular block is requested from the disk more than it should be. A reasonable approach is to turn on verbose operation and write a small test requests file with which you can trigger the error. Then you'll be able to see what's going on and use that to debug the problem in your code (or at least point you in the right direction).
Keywords: assess5-1314
Referrers: Question 30 (2013) , Question 57 (2013) , Question 66 (2013) , Question 76 (2013)
Submission reference: IN2871
With EMAS, say that you connect to a file and at first the mode you want is read, but later on you decide that you want to write to it, will it make another connect ion to the file so the same file will have two different Virtual Addresses in the Virtual Memory or will you disconnect from the the original address you are reading from then open and new connection with a write mode?
You can just change the existing connection mode to read/write.
Submission reference: IN2870
What is meant by operator messages and operator commands below? 'usually, the user’s terminal acts as a virtual control console, so that all operator messages are displayed at the terminal, and all operator commands read from it'
The system is emulating a 'mainframe' style computer. This may have several users as well as a central 'operator' who oversees it. So the 'operator console' is for overall management. In 'olden times', this would have been a special terminal in the computer room.
Submission reference: IN2873
With set associative caching so if you do it 4-way can each bit of cache have different cached addresses on them, or do they all have to be the same?
Each of the 4 caches can have different addresses (and data) cached — and necessarily so, else the collisions that a direct mapped cache experiences wouldn't go away! In a 4-way set-associative cache, there 3 other caches to choose from if 1 is already occupied on the particular line that address maps to.
Keywords: cache
Submission reference: IN2874
In assessment 5, where is the read-write head initially at?
Look in DiskSim.java! (but to save you searching through that, it's on track 0).
Keywords: assess5-1314
Referrers: Question 54 (2013) , Question 67 (2013)
Submission reference: IN2875
I am correct in assuming that to create a circular scan within the assessment you could sort the request queue, go through this queue, sending each block to the disk to be read, and once all blocks have been dealt with go back to the beginning of the queue and deal with blocks that have been added since the last scan?
That would mostly work, but probably not in the most efficient way. What you cannot do, however, is have a loop that sends all the requests to the disk one after another — requests to the disk to read a block have to go one at a time, and as the FIFO (and LIFO) code shows, this means the next request is dispatched when the previous one has finished (and the system calls DSched.readcomplete(...)). Back to the original point, though, if you process one queue of requests whilst building a second, you might miss the opportunity to read blocks as you pass them in the request queue, but on the other hand, such an approach might give shorter service times in general, as there'll be less in the request queue (depending on the workload).
Keywords: assess5-1314
Submission reference: IN2877
What are logical errors caused by in the assessment?
They are caused by something going wrong: the assessment description says serious errors. I.e. any errors mean your scheduler is doing something wrong (usually returning a block that was already read, or a block that was never requested). In such cases, an error message will have been emitted already stating the specific cause of the error (or at least the resulting symptom of it).
Bottom line: if your solution has errors, it is broken, and any results produced are invalid. Such submissions will probably not score highly (plus I'll have to look at them individually, which may take time).
Keywords: assess5-1314
Submission reference: IN2878
What does this error mean?
highlevel_didread(): read queue 12 got unexpected block 8228500
This is probably caused by the same thing as Question 23 (2013). In this case, it means the high-level code got back a block that it wasn't expecting, possibly because it had previously requested and got it. As in the other case, errors of this kind are usually caused by queue mismanagement.
Keywords: assess5-1314
Referrers: Question 57 (2013) , Question 79 (2013) , Question 81 (2013) , Question 98 (2013)
Submission reference: IN2879
Is there anything in particular we should be prepared for on the exam? Is there anything specific that we should be studying?
The bottom line is pretty much everything, unless we've explicitly said that it's non-examinable (at the time in a lecture, for instance). Past papers (linked on moodle) will give you a good idea of what sorts of questions to expect. The architecture half of the module has changed this year, so I'll put together some mock questions based on the new content in the next week or so. It's worth bearing in mind that we expect you to spend in excess of 40 hours, on average, revising for this module — and similarly for other modules. The exam will, of course, test understanding as much as knowledge, so just attempting to fill your brain with facts isn't a good strategy here — there needs to be an understanding built on that knowledge.
Keywords: exams
Submission reference: IN2880
What are the block request queues?
These provide the blocks that need to be read by the disk (scheduled by your scheduler along the way). In the request files, each useful line defines a single request queue, that consists of a sequence of block numbers. The simulator will try and request several blocks from each queue simultaneously, requesting new ones as old ones are completed.
Keywords: assess5-1314
Submission reference: IN2885
For the assessment are you allowed to use the array clone function?
No — if you want that functionality, you'll have to write it yourself, but in this sort of situation there shouldn't be any reason why you would need to do this: copying arrays of things is expensive and isn't the sort of thing OS code would normally do.
Keywords: assess5-1314
Submission reference: IN2887
Are we allowed to assume the number of tracks is fixed, allowing us to use DiskSim.NTRACKS?
Yes, that's fine — do use DiskSim.NTRACKS though, in case it does change (though it won't be changing at run-time!).
Keywords: assess5-1314
Submission reference: IN2886
Looking at the code for assignment 5, does this line:
readqueue = new ReadReq[DiskSim.MAXREQUESTS];
add all of the blocks to read to the queue?
Also, if I am to implement a Shortest Seek Time First (SSTF) algorithm, does a queue have to be used?
Not quite. This line just allocates a fixed-size array of 'ReadReq' object references, enough to hold the maximum number of requests that the system might ask for (in real systems this may be unbounded [available memory permitting] but is fixed for the purposes of this simulation — to avoid the need to write code that dynamically resizes arrays). Note, though, that this line does not allocate any 'ReadReq' objects themselves, they get allocated and placed in this array a few lines of code along.
Regardless of the algorithm implemented, your code needs somewhere to store the requests. In the code given, this is just that fixed-size array, plus head&tail pointers and a size that make it into a queue (technically, a circular buffer). You could just treat the array as a stack (like the LIFO implementation, provided, does) or use something else — up to you! The FIFO implementation uses a circular buffer because that is the simplest in this case — first in, first out. LIFO uses a stack for the same reason, last in first out. SSTF and other algorithms, that may need to re-arrange requests or supply them to the disk in a different order, might make use of something like a linked-list (which is effectively what the circular buffer provides when implemented in an array rather than a list with "next" pointers). But this assessment is not about writing mergesort or other complex algorithms! Bear in mind that the execution efficiency of your code is less important than the effect it has on the simulated performance (i.e. you could write a highly efficient disk scheduling algorithm, that performs well in all the tests, but which in itself is inefficient — to the extent of could-be-better rather than is-2+-orders-of-magnitude worse).
Keywords: assess5-1314
Submission reference: IN2888
For the disk scheduling assessment, can we use exceptions?
No: on the grounds that normal OS languages do not have these (i.e. C and assembler). Whilst it can make programming a bit more interesting (error checking and handling needs a bit more thought perhaps) it is realistic.
Keywords: assess5-1314
Submission reference: IN2889
On slide 11 of the lecture "AVR & Assembly Programming", what do you mean when you say that the instruction can't be encoded?
I thought the SRAM just contained data+registers for the instruction to use; why would the instruction be encoded onto it?
And what's X, Y and Z?
For context, the slide (talking about SRAM access) states: "need 16-bit (or at least 12-bit) addresses — not enough room to encode in instructions.". The issue here is that instructions themselves (e.g. load or store) cannot refer to SRAM addresses directly — there isn't enough room in a 16-bit instruction word to encode a 16-bit (or 12-bit) address (plus whether the instruction is a load or store and the target or source register).
SRAM just contains data — no registers, although the contents of the register file are accessible at SRAM addresses 0-31, this is a convenience for programming: when code accesses these locations, no real SRAM activity takes place (because the actual 2 kilobyte SRAM is mapped at addresses 0x100 to 0x8ff). However, there is nothing about encoding instructions onto it (that doesn't make technical sense), the issue as stated is how to represent the possible addressable locations (0x000 to 0x8ff) in a read or write (or other) instruction to be able to access this memory from the program.
The X, Y and Z registers are just particular names for pairs of 8-bit registers, that are used to provide 16-bit addresses. The main use being to access SRAM. I.e. you load a 16-bit address in two halves into the appropriate X, Y or Z register, then say to the CPU "load from address in X". That way the instruction only has to encode whether the address is in the X, Y or Z registers, not the actual address itself. Reading and understanding the various assembler examples (including those from the practical session) will help to put some of these aspects in context.
Keywords: avr , architecture
Submission reference: IN2890
Can we assume for() loops are acceptable in the assessment?
Yes, as are while() loops, and the use of continue and break as necessary. foreach() loops are not allowed, however.
Keywords: assess5-1314
Submission reference: IN2891
If input is high/1/Vdd and there are two transistors will the lower one always be the one which is switched on? Is this because high is dragged to low because Vdd always flows to Vss and vice versa?
Finally, are things like gates built on top of a diode which allows the current of the gates to only flow one way?
With regard to your first question, it's not entirely clear what you're talking about here! It sounds like you are asking about something like the 'not' gate (inverter) from lecture 2. In this sort of setup, and as explained on that slide, one of the transistors is always on and one one is always off, assuming the input is in a steady-state (itself 1 or 0). Current flows as a result of potential difference, so if both the transistors were ever on simultaneously, there would be a short circuit from Vdd to Vss through those transistors — held for any appreciable amount of time, this will undoubtedly destroy the circuit. When something like an inverter switches, there is usually a brief period (nano-seconds) of short-circuit — either direct or from capacitance inherent in the circuit: thus, switching costs power.
Regarding diodes and transistors, see lecture 1. Logic gates (e.g. and/or/not) are built out of transistors (see lecture 2), and may contain diodes as extra bits if needed, but not always. Both BJT and FET transistors act as diodes in some sense (see any introductory electronics texts/Wikipedia/etc.) but as far as building digital circuits goes, transistors (used to build gates) and diodes are quite different.
Keywords: electronics
Referrers: Question 41 (2013)
Submission reference: IN2892
What is a transistor with a small circle next to it? As in the third transistor from the top in output latch slide of the second lecture.
It's just another transistor, but of the other type. I.e., here there are 3x n-MOSFETs and 1x p-MOSFET. See the description in lecture 2 for the difference.
Keywords: electronics
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Maintained by Fred Barnes, last modified Wed May 25 15:07:20 2016 |
