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CO527 Anonymous Questions and Answers |
This page lists the various questions and answers. To submit a question, use the anonymous questions page. You may find the keyword index and/or top-level index useful for locating past questions and answers.
We have taken the liberty of making some minor typographical corrections to some of the questions as originally put. Although most of the questions here will have been submitted anonymously, this page also serves to answer some questions of general interest to those on the course.
Submission reference: IN3722
Are we allowed to use any of the following: if statements; if else statements; while loops; foreach loops?
Yes; yes; yes; no. The first three are things that work on primitive types (booleans in this case). The last typically works on collection classes. Regular for-loops, on the other hand, just work on primitive types (boolean again, as the test for executing the loop body), so are perfectly fine. foreach and for loops are very different things.
Keywords: disk-scheduling
Referrers: Question 48 (2014)
Submission reference: IN3723
I am planning to implement C-SCAN, but am hitting some issues.
Are we allowed to write private classes, like ReadReq, inside our DSched class? Also, how can I find out what position the disk head is in? Should I assume it starts at 0?
Writing private classes for the purposes of creating data-structures is fine, but these should be no more complex than the level of "ReadReq". I.e. no inheritance, overriding, templates/generics, etc. These things are very much high-level OO features, and not something the typical OS programmer would have (nor want for efficiency) to use.
As far as assuming the disk heads always start on track zero when the simulation (disk) starts, that's a safe assumption (and realistic as most disks probably put the head here after spin-up and self-tests).
Keywords: disk-scheduling
Referrers: Question 43 (2014) , Question 44 (2014)
Submission reference: IN3724
I have implemented my algorithm using a modified LinkedList that I have written myself as a private class inside DSched.java. Am I okay to submit this since technically it isn't a Java collection class.
Yes, that's absolutely fine, provided you are only using it in the basic (data-structure) sense. As mentioned in Question 42 (2014), no implementing 'Iterator' interfaces, exceptions, etc.! (and I'm not bothered if you want to make all fields public and access them directly, as these are imitating data-structures and, given the simplicity, filling the code with accessors/mutators is overkill).
Keywords: disk-scheduling
Referrers: Question 44 (2014)
Submission reference: IN3725
Can we make use of OO by making our own inner classes inside of DSched, and if so, how complex can they be?
I'm not sure how I'm going to implement my preferred algorithm, but it might be helpful to make a data structure, like linked lists or tree maps, only in my own code, rather than relying on the Java library.
You can make use of inner-classes as data-structures, but no OO-specific features please! Real OSs obviously do have things like linked-lists, trees, hash-maps (and a whole lot of more complex stuff), which you're perfectly fine to use, provided you implement them yourself and keep it simple (no inheritance/overriding/polymorphism/interfaces/exceptions/...). See also the answers to Question 42 (2014) and Question 43 (2014).
Keywords: disk-scheduling
Submission reference: IN3726
Will both of these loops iterate through the circular queue correctly?
[snip code loops]
This is something you should discover for yourself perhaps! Getting into the habit of writing small programs to figure these things out will make you a better CS-er :-). Or working it out by hand on paper equally as good; draw out a very small circular buffer (4 entries say) put stuff in, take stuff out, see if you loop algorithms behave the same (and/or do the intended job). As a hint, those two loops are not equivalent in the context of a circular queue of length DiskSim.MAXREQUESTS.
Submission reference: IN3728
My sorting algorithm doesn't quite work, it uses a nested for loop. I understand how to iterate over a circular queue with one for loop, but it would appear you can't just do the exact same thing for a nested for loop. Any tips?
Yes, don't use a circular queue! The circular queue's only use is for FIFO, if you're implementing something different (or at the very least sorting its contents) the circular nature of it just makes things hugely more complex. For most things, starting from the LIFO code example makes more sense.
Keywords: disk-scheduling
Submission reference: IN3727
My C-scan implementation gets 680 on "requests.txt" and 3940 on "requests-big.txt", I don't really understand why it's getting such bad results on the big file? Do you have any advice? Basically every time a block is added to the queue I bubble-sort it. Would I be better off giving an SSTF implementation that gets 686 and 3130?
From the sound of it, there's something not quite right with your C-scan. The "reference" implementation of C-scan gives a result of around 2340 on "requsts-big.txt" (and a non-circular-scan only slightly worse). Maybe create some more test data files and see how those fare, but given the value you report, I think there's something wrong with your implementation.
Referrers: Question 49 (2014)
Submission reference: IN3729
It is mentioned we cannot use foreach loops, but DSched.java has a for loop that populates the array with ReadReq instances. Are we allowed to use for loops?
Yes. See also Question 41 (2014).
Keywords: disk-scheduling
Submission reference: IN3730
My C-Scan solution gets 798 on the small file, 4235 on the big file which seems worse than SSTF but on --dynamic 32 it is around 3000. Is something going wrong? Will I get a better mark for submitting this than SSTF which gets 700ish on small, 3000ish on big and averages around 5000 to 12000 on --dynamic 32?
Difficult to say outright. The numbers you give suggest SSTF will net you a better score, and 3000 ish for SSTF on the requests-big.txt file is sensible. See also Question 47 (2014).
Submission reference: IN3732
If I attempt the assessment but it does not work/compile, do I get 0.
Not necessarily. Typically I'll look at the code to see what you were probably attempting to do. These will score less than 50% however.
Submission reference: IN3733
I've done the CScan method and get around 2400 for requests-big.txt which is good, however I get ~780 for the requests.txt does that mean I've done something wrong or is it just worst for smaller sets of data?
Neither. Performance ultimately depends on the specific requests, not how many of them there are. But that value for the smaller requests file isn't overly bad (my implementation of C-scan gives around 670). My 'scan' implementation (non-circular) gives more like 800 for the small requests file, around 2400 still for the big requests file.
Keywords: disk-scheduling
Submission reference: IN3734
I'm still trying to get SSTF working, do you have any advice on how to tackle an error such as "read queue 0 already done at time 489 (block 0)"?
This is typical of reading and returning a block that had been read previously. I.e. check that when you dispatch a read request to the disk, that it is that one which is removed from the request queue/array. I've seen various examples of code that fails because of this (with different errors depending on the circumstances). As a general point though, if you're using the circular queue code, get rid of it and use the LIFO (stack) code as a basis — it's a lot simpler!
Keywords: disk-scheduling
Submission reference: IN3735
For assessment 5 I want to implement SSTF, but have no idea where to start first. I understand the algorithm, but don't know where to start implementing and what code to write; is there any material that can help me?
It's somewhat late in the day to be starting this assessment really :-(. But I'd suggest starting with the LIFO version of the code (that does not have any circular buffer stuff in it, which is somewhat confusing if you're not comfortable with it). When there are more requests to dispatch, this just dispatches the one at the end of the request array (which will be the most recently arrived request). For SSTF, you'd need to modify this code to find and dispatch the request whose track is closest to the one most recently serviced. There's some pseudo-stuff in the slide-deck (see Moodle) that should help with implementing this. Also these anonymous Q+As, of which a lot of the recent ones are related to the assessment.
Submission reference: IN3736
When it says we need to save the last requested block number, but then to update it again when it's done reading, what are we supposed to make of that?
Exactly that. I.e. if you're implementing something like SSTF (shortest seek time first) then you need to know what the last position of the disk heads was, so when you're looking for another request to send to the disk, you've got something to base a comparison on. But more to the point, it's something you need to keep track of yourself, and not rely on the value of "blk" passed to "readcomplete" as that may be less than zero (disk idle, ready for request) in some cases.
Submission reference: IN3737
I've tried to implement CSCAN with linked lists, and I'm getting lots of pending queues; where in my code should I be looking for errors? I've run through things a few time on paper and I can't work out what's going wrong.
Losing requests is the main cause of this sort of error. I.e. when you're adding and removing from the list, something is going wrong. Mis-management of head and tail (or first and last) pointers is a typical problem.
Submission reference: IN3740
Which lecture is the difference between a process control system and an embedded system talked about?
I can't remember off the top of my head — look through them? :-). This is a good example of "stuff you should be able to find out for yourself"!
Submission reference: IN3741
You would use the cache disable bit for memory mapped hardware right? I don't really know how to explain why though. Because it doesn't actually refer to memory and can't be treated as such, therefore it doesn't make sense to cache it? Or that its different each time and so cache doesn't make sense? Also, is it just memory mapped hardware you'd want to disable cache for?
Memory-mapped I/O regions (e.g. PCI space) are sensible to cache-disable for the 2nd reason you give. The first "because it isn't memory" probably wouldn't earn you marks in an exam as it lacks an explanation as to why. But "different each time" is wrong (though some marks for that). The precise reason is that "it might be different each time it is read" and writes to I/O regions must go straight to the bus (e.g. timing requirements) and not be delayed in a write-back cache, for instance. Other memories that don't make sense to cache: graphics framebuffer. Or at an application-level, a clever programmer (who knows how their program works) could turn off cache for regions of virtual memory that they know aren't worth caching based on the access characteristics. You might also want to turn off caching to work out the performance gain the cache is giving you (but that's a more all-encompassing, less page-level, reason).
Keywords: cache , memory-management
Submission reference: IN3745
The following diagram shows the bit values of a Branch if Equal instruction located at address 0x0000CF00, and the contents of a selection of registers in the Register File:
[snip]
- Could you give me help/tips on how I would approach this problem ?
No :-). Try and figure it out for yourself, ask a friend, or failing all else, come and ask me. Based on the question, did you attend any lectures? (or slept through them) — I'm not being sarcastic :-).
Submission reference: IN3751
For the ATMega328, if the data address space 16 bits, that means there are 65536 addressable locations within it, each of which is 8 bits in size. So overall there is about 64kb of SRAM. I'm getting a bit confused. Am I right in saying that the data address space is only 16 bits when there is 64kb of SRAM, and if there was, say, 2kb of SRAM, the address space is just 11 bits?
There are two aspects here which you're confusing slightly. The first is the size of the address space, and as you point out, a 16-bit address space can address exactly 64 KiB (216) addresses. The second aspect is how much memory (SRAM) there actually is. So on something like the ATMega328, the address space is 16-bit, but only 2 KiB of it is actually occupied (attempts to access things in the remaining 62 KiB won't result in any sort of error, probably either garbage [random] data or mapped onto the 2 KiB SRAM repeatedly, which I think the AVR actually does, but check the datasheet if you want to be sure!).
Because the ATMega328 only has 2 KiB SRAM, you'd only need 11 bits of address space for practical purposes. If you look in the datasheet, some address-specific I/O registers only actually have enough bits as needed (e.g. the stack-pointer is 11 bits on the ATMega328, more on the ATMega2560 for instance).
Keywords: avr , architecture
Submission reference: IN3752
How do we have 16-bit values flying around the diagram of our processor near the program counter when it's just an 8-bit machine? Is it just that those particular address buses are wide enough to allow it, or are we using the value held in 2 8-bit registers?
This is explained in one of the OS lectures probably: the "8-bit"-ness of the machine (word size) refers to the natural size of computations in the device. But that doesn't preclude different bits of the architecture having more (or less) bits. The program memory is a 16-bit space (actually more on some devices) so the address busses involved here are suitably sized. The fact that the instructions come out of the program memory in 16-bit pieces is co-incidence (mostly). Because the registers are only 8-bits wide, when manufacturing a complete address in the program, you'll need to pair up 2 8-bit registers (which is kinda what the X, Y and Z register pairs are for).
As a fairly crude contrast, something like the Intel Pentium (old now), was a 32-bit processor, but had a 36-bit (physical) address space, 32-bit (virtual) address space, and the instructions in memory vary in size between 1 byte and 7 bytes (give or take).
Keywords: avr , architecture
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Maintained by Fred Barnes, last modified Wed May 25 15:07:20 2016 |
